Celoxica Accelerator for Market Data

Celoxica offers a radically new approach. Ultra high speed is attained by using co-processors which not only offer the fastest possible network data rates but allow data translation and filtering in parallel at virtually zero cost in latency.

Our first feeds are available for:

International Securities Exchange (ISE) Options

OPRA

NASDAQ (ITCH)

Our product is designed to integrate simply with existing trading applications and is offered on standard servers through standard programming interfaces. The solutions are designed to easily take advantage of future developments in accelerated computing as well as the investments of the major players in the chip and server market.

In addition to the hardware, firmware and IP, we offer services to continuously maintain compatibility with the market feeds which we support – even as formatting or protocol changes are introduced by the Exchanges.

base_market_data

In this diagram, the Celoxica RCHTX card demonstrates the same latency, regardless of the network load and the size of the packet. The Ethernet Card manages to give consistent latency for larger packets, but cannot keep up with bursts of smaller packets.The steep lines for 64, 128 and 256 byte packets show that the latency increases very quickly as the system has to buffer packets and rapidly starts dropping packets in these cases. No buffering is necessary with Celoxica's RCHTX.

Low-Latency, High-Capacity Market Data Capture

Celoxica's Accelerator for Market Data Capture (AMDC) is the first product on the market to offer ultra-low-latency access to market feed data. With average latency figures in single-digit microseconds, Celoxica is redefining the term “low latency”.

Celoxica leverages hardware acceleration to provide an innovative new architecture for access to market data feeds. Integrated into  standard, Tier 1 OEM servers, the Celoxica AMDC offers the ultimate combination of performance and ease-of-use.

Key Benefits

Lowest-latency access to market data feeds

Capacity for 2009 message volumes

Minimal impact on heat and power consumption

Non-intrusive, dramatic increase in performance of standard servers

Co-procssor diagram

A co-processor directly connected to the network port means that the AMDC can provide consistent low-latency which does not depend on the volume of data. The HyperTransport link to the host CPU provides the lowest latency bus transfers available in standard servers.

Hardware protocol stack (TCP, UDP, IP) - No overhead typically associated with software protocol stack

Hardware FAST decoder

Hardware conversion from FIX messages to binary representation

Automatic, hardware recovery via secondary feed and TCP link

HyperTransport interface to the host CPU offers the lowest latency co-processor to CPU communications on the market

Best Case, average case, worst case + percentages of messages that fall under these for each feed, with fragmented datagrams

Capacity

The innovative architecture of the AMDC means that it can deal with message volumes predicted for 2009.

Each AMDC can process 2 saturated 1 Gbps Ethernet links with no impact on latency

Maximum ~10M FAST Messages/second combined A/B feed

Never drops a single packet, regardless of link load

Minimal impact on heat and power consumption

The low-power co-processor architecture means that even when processing two fully-saturated 1 Gbps network links, the total power consumption of the server is barely affected.

Consumes ~25 Watts processing fully-saturated links

Non-intrusive, dramatic increase in performance of standard servers

Simple integration into existing applications on standard servers, with the ability to customise the message interface.

Qualified and supported by standard Tier 1 OEM server vendors (HP, IBM)

Uses standard rack-mount servers

Standard, readily-available slot form factor

Simple C/C++ API for integration into existing applications

NIC emulation for diagnostics and integration into IT infrastructure

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